Thin polished plates such as silicon wafers and the like are a very important part of modern technology. A wafer, for instance, may refer to a thin slice of semiconductor material used in the fabrication of integrated circuits and other devices. Other examples of thin polished plates may include magnetic disc substrates, gauge blocks and the like. While the technique described here refers mainly to wafers, it is to be understood that the technique also is applicable to other types of polished plates as well. The term wafer and the term thin polished plate may be used interchangeably in the present disclosure.
Wafer processing industries aim at integrating more circuits on a smaller chip at a lower cost with the ability to manufacture chips in large volumes with high quality and reliability to continuously improve the yield. As semiconductor technology evolves toward smaller and smaller nodes, wafer test metrology equipment is crucial to process development and to control that the wafers are in good quality. If a wafer has been damaged by previous processing steps, it is scrapped rather than undergo further processing to save money and time.
Nanotopography is defined as the deviation of a surface within a spatial wavelength of around 0.2 to 20 mm. Nanotopography bridges the gap between roughness and flatness in the topology map of wafer surface irregularities in spatial frequency. Nanotopography of the silicon wafer is dictated to a large extent by the polishing process. A true planetary, freefloating, double-sided polishing process that simultaneously polishes both sides of a silicon wafer technically achieves the required nanotopography and flatness results.
Nanotopography and flatness monitoring are critical at different steps in the wafer manufacturing process. The nanotopography and flatness of incoming bulk wafers are key parameters because of their impact on final wafer properties and wafer bond ability. Since the flatness properties of incoming 200- and 300-mm wafers undergo only minor changes during wafer processing, precise and comprehensive measurement capabilities are necessary to detect minute variations in topography on the final wafer surface.
Presently, the wafer metrology tools, such as WaferSight from KLA-Tencor, can scan both the front and back surfaces of a wafer, which is held vertically to avoid gravitational deformations. By combining wafer shape, edge roll-off, thickness or flatness, and nanotopography measurements in a single scan, the system provides complete data sets that are necessary for nanotopography and wafer geometry monitoring in wafer manufacturing. The system also performs dual-side topography measurements with high sampling resolution at the wafer edge in a single measurement.
Nanotopography data helps to close the gap between micron- and wafer-scale thickness measurements. Depending on the reference plane definition at the silicon/oxide interface, nanotopography can be linked to top-silicon thickness variations, thus providing uniformity information at the millimeter scale.
The settings of the high-pass or band-pass filters used for nanotopography measurement evaluation may significantly influence the results reported. Height maps of wafers of different nanotopography conditions recorded with an interferometric tool are processed with different filter settings in an experiment with factorial design in order to assess their influence and range of variation. Typical parameters of filter settings include filter type, filter cut-off wavelength and data extrapolation at the wafer edge. It is known that filter type, cut-off wavelength, and data extrapolation have significant impact on nanotopography measurement results. These three factors also are subject to strong interactions. A double Gaussian filter with constant 20 mm cut-off wavelength or variable cut-off wavelengths, starting from 20 mm cut-off wavelength in the wafer interior region and reducing to 1 mm in the wafer edge region are often used for providing accurate nanotopography height maps. Application of deviation metric for threshold height analysis allows the correct localization of peaks and valleys in the map and determining defective areas on a wafer.
The old method uses the Gaussian or Double Gaussian (DG) filters to process the wafer surface image and then calculate the specified metric values over the sites of the filtered images. However, the Gaussian and Double Gaussian filters have large attenuation on the signals from certain features of interest, dimple/pit, edge EPI crowns, scratch and slipline. Dimple/pit refers to surface depression. Edge EPI crowns refers to the difference between the surface elevation from the edge of the slice and that of the slice edges exposed in microns (associated with EPI layer deposition). Scratch refers to a shallow groove or cut below the established plane of the surface. Slipline refers to a process of plastic deformation in which one part of a crystal undergoes a shear displacement relative to another in a manner that preserves the crystallinity of each part of the material.
There is a large residue of low frequency shape component in the filtered image when the cutoff wavelength of the filter is long, making the old method that uses the Gaussian or Double Gaussian (DG) filters unsuitable. In addition, the response of the Gaussian and Double Gaussian filters to the wafer edge roll-off and the discontinuity created from edge exclusion also hinders the accurate identification of the wafer surface features in the wafer edge region.
Therein lies a need for systems and methods of advanced site-based nanotopography for wafer surface metrology without the aforementioned shortcomings.